Discrete transistor probing has become an extremely difficult task as device feature size and pitch have shrunk. As predicted by Moore’s Law, the transistor’s minimum feature size is now well below the limits of optically based probing. For standard 6T SRAM cell layouts, the cell area may be under 4µm². The SEM micrograph on the left shows the tungsten contacts and poly gate finger of the N channel transistor within the SRAM array. The gate length is 90nm and the width is 300nm. The contacts are about 210nm in diameter with a mimimum pitch of 300nm.
This has forced analysts to resort to probing within SEM or FIB chambers. (See below for disadvantages to these methods.) The average success rate of adding FIB pads is typically less than 20%. The Atomic Force Probe provides an alternative. The AFP uses the proven non-destructive technology of the Atomic Force Microscope to provide an image resolution of less than 5nm.
The ultra-sharp tungsten needles of the AFP provide a tremendously long lifetime along with very low ohmic contact with the sample. With a positioning accuracy within 5nm, the AFP gives the user the ability to place the probes on the desired nodes very quickly with controlled contact force allowing for standard device characterization.
- SEM Radiation Damage
- SEM used to document location for 3-Probe AFP Measurement (top image). Subsequent AFP of same area shows damaging effect of the SEM on devices (bottom Image).
- END CUSTOMERS:
- Process Engineering: Relate process to properties
- Device Engineering: Baseline technology
- END USERS
- Product Engineering: Categorize failures
- Failure Engineering: Characterize defects
- Disadvantages of FIB probing pads:
- The preparation effort is very high.
- On densely packed layouts the preparation is error-prone because the spacing is too narrow for reliable FIB contacting.
- There is a considerable risk of transistor parameter drift by implantation of Ga ions [4,5].
- The access to circuit nodes is quite limited. It is hardly possible to measure more than one transistor inside of a cell because the FIB probing pads cover the adjacent transistors.
- Traditional micro-probing techniques have become inadequate for root-cause failure analysis of shrinking device geometries
- FIB turn-around-time for a single transistor ~3 hours
- Insulator deposition needed for isolation of probe pads
- FIB contact end-point detection difficult on SOI @ <5pA I-beam
- Average success rate of FIB probe pads is 20% on 130nm
- Impossible to probe entire 6T bitcell in L2 (90 & 130nm)
- FIB of SOI material drastically alters FET characteristics
- Multiple parametric tests have caused opens on SOI (blown gates?)
- UV or bake step necessary to bleed off ion-beam trapped charge ~1/2 hour
- FIB pads complicate further deprocessing
- Disadvantages of SEM probing:
- Due to the lack of a force control mechanism, sample and probe needle are exposed to high mechanical stress.
- Surface contamination by the electron beam might lead to contact problems.
- Contacting and measurement is error-prone on small geometries because the contact point of the probe tip is not visible in the e-beam image.