Technical Publications

Calibration of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS)

Terence Kane and Michael P. Tenney, IBM Microelectronics, Hopewell Junction, New York, USA
Andrew Erickson, and Peter Harris, Multiprobe, Inc., Santa Barbara, California, USA

Abstract: CV curve analysis has been the primary metric for gate oxide properties. Test structures designed for CV measurements are used to measure oxide and doping properties of a process because the gate capacitance of a single transistor is far too small to measure with available analyzer equipment. Meaningful nanoprobe CV characterization of discrete MOSFET devices requires the development of a capacitance measurement tool with sufficient sensitivity and accuracy to measure structures with capacitance of less than one femtoFarad. The resonant sensor used for scanning capacitance imaging is known to be able to measure capacitance changes at this level [9]. The tools that have been commercialized to do capacitance imaging have not been applied or optimized to allow for discrete device CV measurements. However, an updated version of the resonant capacitor design operating at about 1 GHz, has been integrated into an Atomic Force Prober system.

Challenges of Atomic Force Probe Characterization of Logic Based Embedded DRAM for On-Processor Applications

Terence Kane, Michael P. Tenney, IBM Systems and Technology Group, Hopewell Junction, New York.
Andrew Erickson, Sebastien Phan, Multiprobe, Inc. Santa Barbara, California

Abstract: Nanoprobing logic based SOI embedded DRAM cells for onprocessor designs poses different challenges than probing conventional six transistor SRAM designs. This paper will describe nanoprobing logic based embedded DRAM (eDRAM) cells in 65nm SOI applications. We will also describe probe placement and measurement methodology for electrical characterization of leakage between deep trench capacitors composing those eDRAM designs. The introduction of nano CV metrology and scanning capacitance imaging for use in characterizing DRAM capacitors will also be discussed.

Atomic Force Probe Kelvin Measurements of Large MOSFET Devices at Contact Level for Accurate Device Threshold Characteristics

Terence Kane, Michael P. Tenney, IBM Microelectronics, Hopewell Junction, New York.
Andrew Erickson, Sebastien Phan, Multiprobe, Inc. Santa Barbara, California

Electrical Characterization of sub-30nm Gatelength SOI MOSFETs

Terence Kane and Michael P. Tenney, IBM Microelectronics, Hopewell Junction, NY

Abstract: Demonstrations of sub 20nm gate length MOSFET devices involving various FEOL (front end of line) schemes such as Silicon On DEpletion Layer (SODEL) FET´s, asymmetricgate FinFET devices, planar Ultra-thin body SOI (UTSOI) FET´s, and, more recently, independently oriented surface channels for (110) pMOS and (100) nMOS described as Simplified Hybrid Orientation Technology (SHOT).[1-4, 7-18] have been reported.

Atomic Force Probe (AFP) techniques are particularly suited for electrical characterization of sub-65nm node SOI devices with multiple metal interconnect levels and low-k back end of line (BEOL) interlevel dielectric films. AFP electrical measurements of sub-30nm gatelength SOI MOSFET devices will be described.

Current Image Atomic Force Microscopy (CI-AFM) combined with Atomic Force Probing (AFP) for location and characterization of advanced technology node.

Tom X. Tong, Intel Corporation, Hillsboro, OR
A. N Erickson, MultiProbe, Inc. Santa Barbara, CA

Abstract: Many of the standard techniques of Failure Analysis (FA) are breaking down or becoming less useful as feature sizes drop below 100nm. The tenth micron milestone appears to be a fundamental limitation to many common techniques. Use of Current Image-Atomic Force Microscopy (CI-AFM) combined with Atomic Force Probing (AFP) brings about a combination of technologies, which allow for extension of FA below the nano-scale.

Advanced electrical analysis of embedded memory cells using Atomic Force Probing

M. Grützner, Department of Failure Analysis, Infineon Technologies AG, Munich, Germany

Abstract: To identify the failure cause of embedded memory cells - e.g. SRAM with 6 transistors - it is often necessary to measure the electrical parameters of each transistor. Until now, on integrated circuits with small feature size and pitch, this was only possible using FIB probing pads or SEM probers, but both methods are complex and error-prone. Today Atomic Force Probing (AFP) provides a powerful alternative, allowing fast and non-destructive characterization of single transistors. In this paper the functional principle of the technique is introduced. Three case studies of SRAM, ROM and NVM cells illustrate the successful application of this nano probing tool.

Combination of SCM/SSRM analysis and Nanoprobing technique for soft single bit failure analysis

Larry Liu, Yuguo Wang, Hal Edwards, David Sekel, and Dan Corum, Texas Instruments Inc. Dallas, TX

Abstract: Traditionally, many semiconductor companies have used SRAM memory to develop their process technologies. The job of the failure analyst is often to physically deprocess the sample and hope to find the defect with only the bit map location to guide them. The success rate has been better in the past when the size of these SRAM cell were bigger. With the technology shrinking every 2 years, the chance of finding physical defects has become less and less.

Besides the shrinking SRAM cell geometries, the electrical failure signature for many of the failures is marginal (soft failure), presenting difficult challenges for failure analysis (FA). Physical analysis of these soft SRAM failures at the sub-100nm technologies is often non-visual without detailed isolation and electrical characterization. Therefore, additional techniques are needed to improve the successful FA on newer technologies. In this discussion, we will present the uses of both SCM/SSRM (scanning capacitance microscopy / scanning spreading resistance microscopy) analysis and nanoprobing technique for fail site isolation.

Atomic Force Probing in Analog MOSFETs Measurement

Kaiyuan Chen, Tathagata Chatterjee, Kim Christensen, Juan Rosal and Hal Edwards, Texas Instruments Inc, Dallas, TX, USA

Abstract: Accurately measuring parameter mismatch for analog MOSFETs, such as the threshold voltage (Vt) or W/L ratio, is often required in analog circuit failure analysis. The challenge in probing analog MOSFETs using atomic force probing (AFP) is contact resistance. Contact resistance between AFP tips and tungsten contacts can cause large error at high current. This paper discusses measurement error caused by contact resistance and the techniques to identify and reduce the contact resistance effect.

Focused Ion Beam Method for Reconditioning Worn Tungsten Atomic Force Probe Tips

Randal Mulder, Sam Subramanian, Tony Chrastecky, Freescale Semiconductor, Inc; 6501 William Cannon Drive, Austin, TX, USA

Abstract: The purpose of this paper is to demonstrate how worn tips that no longer image and probe properly can be reconditioned using the Focus Ion Beam (FIB) tool. Tungsten tips as large as ~750nm can be sharpened down to 100nm and reused for AFP imaging. This method for reconditioning tips is straightforward and requires a minimal amount of time. Typically, four probe tips can be reconditioned in about 30 minutes on the FIB.

Scanning Electron Microscope Induced Electrical Breakdown of Tungsten Windows in Integrated Circuit Processing

David M. Shuttleworth*, Agere Systems, Orlando, Florida
Mary Drummond Roby, Texas Instruments, Dallas, Texas

Abstract: Interaction of inline SEM inspections with tungsten window-1 integrity were investigated. Multiple SEMs were utilized and various points in the processing were inspected. It was found that in certain circumstances inline SEM inspection induced increased window-1 contact resistance in both source/drain and gate contacts, up to and including electrical opens for the source/drain contacts.

Fault Localization in Contact Level by Using Conductive Atomic Force Microscopy

Jon C. Lee, J. H. Chuang, Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, Taiwan

Abstract: As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation.

SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI).

In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.

Scanning Capacitance Microscopy at transistor contact level

Kartik Ramanujachar, Texas Instruments, 12203 South West Freeway, Stafford, Texas, USA

Abstract: Traditionally planar scanning capacitance microscopy has been conducted on samples which have been deprocessed to the level of the substrate and an oxide re-grown over the sample. A drawback of the technique lies in the fact that HF used to etch the sample to the substrate can also dissolve shallow junctions. In this contribution we document the ability of scanning capacitance microscopy to be utilized at the level of the contacts leaving the pre metal dielectric intact.

By deprocessing to this level shallow junctions will still be left intact. We demonstrate the scalability of this technique across three process generations spanning 0.18 micron, 0.13 micron and 90 nm nodes. Preliminary data on anomalous contrast observed in contacts at both 0.13 micron node and 90nm node products is documented. The ability to distinguish between contacts going to a n type diffusion, p type diffusion and transistor gate is demonstrated. Some precautions to be observed when the sample is prepared for this analysis are also highlighted. The final section of the paper discusses a simple conceptual model for the CV curve of a defective contact connected to the depletion capacitance of a source/drain diffusion of a transistor.

Frank Siegelin and Anton Stuffer Infineon Technologies AG, Munich, Germany

Abstract: With high implant doses, strained silicon technologies and shrinking feature sizes, dislocation related failures seem to gain more importance in advanced CMOS devices. On the basis of case studies, different types of dislocations as well as the electrical characteristics of the corresponding devices will be presented.

A New Approach for SRAM Soft Defect Root Cause Identification

Peter Egger, Stefan Miiller, Martin Stiftinger lnfineon Technologies, Otto-Hahn-Ring 6, 81739 Munich, Germany

Abstract: With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top-down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.

Alternating Plane-View and Cross-Section Scanning Capacitance Microscope Technique to Reveal Various Implant Issue

Tsan-Chang Chuang, Cha-Ming Shen, Shi-Chen Lin , Chen-May Huang, Jin-Hong Chou, Jon C.Lee Taiwan Semiconductor Manufacture Company, Ltd., Taiwan. 1,Nan-Ke N, Rd., Tainan Science Park, Tainan, Taiwan 741-44, R.O.C.

Abstract: The International Technology Roadmap for Semiconductors identifies quantitative two dimensional (2-D) and three-dimensional (3-D) dopant profiling as being essential for the advancement of future generations of the semiconductor technology. Currently scanning capacitance microscopy (SCM) is a 2-D carrier and/or dopant concentration profiling technique under development that utilizes the excellent spatial resolution of scanning probe microscopy . It is based on the MOS characteristics between the scanning probe and the substrate and is regarded as having great potential for quantitative 2-D dopant concentration profiling and related framework.

Single Device Characterization by Nano-probing to Identify Failure Root Cause

Chao-Chi Wu, Jon C. Lee, Jung-Hsiang Chuang, Tsung-Te Li, Taiwan Semiconductor Manufacturing Company, Ltd. 6, Creation Rd. 2, Science-Based Industrial Park, Hsin -Chu, Taiwan 300, R. O. C.

Abstract: In general failure analysis cases, a less invasive fault isolation approach can be utilized to resolve a visual root cause defect. In the case of nano technology, visual defects are not readily resolved, due to an increase in non-visible defects. The nor~visible defects result in a lower success rate since conventional FA methods/tools are not efficient in identifying the failure root cause. For the advanced na~ometer process, this phenomenon is becoming more common; therefore the utilization of advanced techniques are required to get more evidence to resolve the failure mechanism. The use of nanoprobe technology enables advanced device characterization in order to obtain more clues to the possible failure mechanism before utilizing the traditional physical failure analysis techniques.

Couple Passive Voltage Contrast with Scanning Probe Microscope to Identify Invisible Implant Issue

Cha-Ming Shen, Shi-Chen Lin, Chen-May Huang, Huay-Xan Lin, Chi-Hong Wang Taiwan Semiconductor Manufacture Company, Ltd., Taiwan

Abstract: In this paper, our objective was to organize a judicious reasoning method by coupling PVC with SPM for revealing particular invisible defect modes, which were imperceptible to observe and very difficult to identify by means of traditional PFA techniques. In order to certify this compound method, it is applied to an implant issue as a case study. Through solving this particular defect mode, whose exact failure position could not be determined even with the most sensitive PVC or highresolution SPM current mapping, the procedures and contentions are illustrated further.

EEPROM Failure Analysis Methodology: Can Programmed Charges Be Measured Directly by Electrical Techniques of Scanning Probe Microscopy?

Christophe De Nardi, Romain Desplats, Philippe Perdu CNES, French Space Agency, DCT/AQ/LE, Toulouse, France

Abstract: A method to measure “on site” programmed charges in EEPROM devices is presented. Electrical Scanning Probe Microscopy (SPM) based techniques such as Electric Force Microscopy (EFM) and Scanning Kelvin Probe Microscopy (SKPM) are used to directly probe floating gate potentials. Both preparation and probing methods are discussed. Sample preparation to access floating gate/oxide interfaces at a few nanometers distance without discharging the gate proves to be the key problem, more than the probing technique itself. Applications are demonstrated on 128 kbit EEPROMs from ST Microelectronics and 64 kbit EEPROMs from Atmel.

Investigation on the Influence of Focused Electron Beam on Electrical Characteristics of Integrated Devices

S. Doering, R. Harzer, W. Werner Qimonda Dresden GmbH & Co. OHG, Dresden, Germany

Combining the Nano-Probing Technique with Mathematics to Model and Identify Non-Visual Failures

Cha-Ming Shen, Tsan-Chen Chuang, Shi-Chen Lin, Lian-Fon Wen, Chen-May Huang Taiwan Semiconductor Manufacture Company, Ltd., Taiwan

Abstract: In this paper, we focus on how to identify non-visual failures by way of electrical analysis because some special failures cannot be observed by SEM (scanning electron microscopy) or TEM (transmission electron microscopy) even when they are precisely located by other analytical instrumentation or are symptomatic of an authentic or single suspect. The methodology described here was developed to expand the capabilities of nano-probing via C AFM (conductive atomic forced microscopy), which can acquire detailed electrical data, and combining the technique with reasoned simulation using various mathematic models emulating all of the significant failure characteristics. Finally, a case study is presented to verify that such defect modes can be identified even when general PFA (physical failure analysis) cannot be implemented for investigating non-visual failure mechanisms.

Analysis of DC Failure in Advanced Memory Devices Using Nanoprobing and Scanning Capacitance Microscopy

Jen-Lang Lue, Chin-Shun Lin, Atup Chiou, Hsuen-Cheng Liao, Hsienwen Liu, Brian Pai, Sam Fan and Tings Wang ProMOS Technologies Inc., Hsinchu, Taiwan, R. O. C.

Abstract: This paper discusses the failure analysis process of a DC failure using an in-FIB (Focused Ion Beam) nanoprobing technique with four probes and a scanning capacitance microscope (SCM) in advanced DRAM devices. Current- Voltage (I-V) curves measured by the nanoprobing technique indicate the curve of the failed device is different from that of the normal device. The failed device causes a high leakage current in the test. The cross-sectional 2-D doping profile of SCM verifies the region of the P-Well has shifted to create a leakage path that causes this failure.

MAXIMUM PERMISSIBLE EB ACCELERATION VOLTAGE FOR SEM-BASED INSPECTION BEFORE ELECTRICAL CHARACTERIZATION OF ADVANCED MOS

Takayuki Mizuno, Miho Takahashi, Yoshie Azuma, Hiroshi Yanagita, Kyoichiro Asayama, Koji Nakamae* Renesas Technology Corp., 5-20-1 Josuihon-cho, Kodaira-shi, Tokyo, 187-8588, Japan Osaka Univ., 2-1 Yamada-oka, Suita-shi, Osaka, 565-0871, Japan

Abstract: The electron beam based inspection instruments such as the Review-SEM are widely used to analyze defects during manufacturing and failure analysis of scaled devices. Nano-probers used for scaled devices analysis also employs SEM for probe guidance. However, electron beam (EB) induced damages are increasing with the scaling. A higher SEM resolution induces device damage. To avoid the damage, the acceleration voltage should be lower. Several generations of scaled devices from 350nm to 65nm were examined, and critical EB acceleration voltage that induced device degradation was quantitatively evaluated. The determination mechanism of permissible electron beam acceleration voltage is clarified.

Application of Atomic Force Probing on 90nm DRAM Cell Failure Analysis

Yu-Ching Yeh*, Chia-Lung Lin, Bi-Jen Chen, Yuan-Wei Tseng, Jeremy D. Russell Physical Failure Analysis Department, Inotera Memories, Inc. No.667, Fuhsing 3rd Rd., Kueishan Township, Taoyuan County 333, Taiwan, Republic of China

Abstract: This article presents a novel method to identify marginal faults in DRAM product via atomic force probing. Failing cells which are difficult to be identified by traditional methods were easily localized by current imaging. In addition, current-voltage curves were useful for judging failure root causes.

Direct Measurements of Charge in Floating Gate Transistor Channels of Flash Memories Using Scanning Capacitance Microscopy

Christophe De Nardi, Romain Desplats, Philippe Perdu. CNES, French Space Agency, DCT/AQ/LE, Toulouse, France. Christophe Guérin DGA/CELAR, French Defense Department, Bruz, France. Jean Luc Gauffier, Thomas B. Amundsen LNMO, INSA Génie Physique, Toulouse, France

Abstract: Failure Analysis has to deal with challenging questions about stored charges in floating gates in Non Volatile Memories (NVM) when reading does not give expected data. Access to this information will help to understand failure mechanisms. A method to measure on-site programmed charges in Flash EEPROM devices is presented. Scanning Capacitance Microscopy (SCM) is used to directly probe the carrier concentration on Floating Gate Transistor (FGT) channels. The methodology permits mapping channels and active regions from the die backside. Transistor charged values (ON/OFF) are measured and localized with a 15 nm resolution. Both preparation and probing methods are discussed. Applications are demonstrated on two different Flash technologies: a two-transistor cell (2T-cell) from Atmel and a one-transistor cell (1T-cell) from STMicroelectronics.

Development of Backside Scanning Capacitance Microscopy Technique for Advanced SOI Microprocessors

Vinod Narang, P Muthu, JM Chin. Device Analysis Laboratory, 508, Chai Chee Lane, AMD Singapore 469032

Case Studies in Atomic Force Probe Analysis

Randal Mulder, Sam Subramanian, Tony Chrastecky Freescale Semiconductor, Inc; 6501 William Cannon Drive, Austin, TX 78735

Abstract: The use of Atomic Force Probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. The purpose of this paper is to present several case studies in regards to these activities and their results.

Conductive Atomic Force Microscopy Application for Semiconductor Failure Analysis in Advanced Nanometer Process

Kun Lin, Hang Zhang United Microelectronics Corporation, Hsinchu, Taiwan, R.O.C. Shey-shi Lu Graduate Institute of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C

Abstract: Conductive Atomic Force Microscopy (C-AFM) is a useful tool for both electrical failure analysis (EFA) and physical failure analysis (PFA). In this paper, the root cause of a physical failure in an analysis image was verified from the evidence of two-dimensional AFM profile depth measurement. The other analysis technique, which is electrical parameter extraction by contacting I-V spectroscopy measurement, was also utilized to locate the possible defects. As a result, the failure mechanism was illustrated with an AFM topography image, which showed the silicon surface profile after removal of cobalt salicide (self-alignment silicide) by dilute HF. The vertical junction leakage path was identified with a C-AFM image.

Deformation Study of Low K Dielectric after E-beam Exposure

Xianfeng Chen, Qiang Gao, Ming Li, Chorng Niou, W.T. Kary Chien SMIC (Shanghai) Corp.18 Zhangjiang Road, Pudong, Shanghai, China, 201203

Abstract: In this paper, the deformation mechanism of low K dielectric film under electron beams (E beams) is discussed, and the effect of film deformation on the development of a low K dielectric film etching recipe is investigated. To provide meaningful data for process development, numerical analysis was used in the failure analysis procedure. A correction factor is formulated to calculate the change in thickness of the low K dielectric film after E-beam exposure. In addition, scanning electron microscope (SEM) settings for imaging low K dielectric films are optimized to minimize deformation.

The Electrical Characterization and Physical Failure Analysis For Transistor Gate Leakage

Tsung-Te Li, Chao-Chi Wu, Jung-Hsiang Chuang, Jon C. Lee Taiwan Semiconductor Manufacturing Company, Ltd. 6, Creation Rd.2, Science-Based Industrial Park, Hsin-Chu, Taiwan 300, R.O.C.

Atomic Force Probe Kelvin Measurements of Large MOSFET Devices at Contact Level for Accurate Device Threshold Characteristics

Terence Kane, Michael P. Tenney IBM STG, Fishkill, New York Andrew Erickson, Sebastien Phan Multiprobe, Inc.

Atomic Force Probe Analysis of Non-Visible Defects in Sub-100nm CMOS Technologies

Randal Mulder, Sam Subramanian, Tony Chrastecky Freescale Semiconductor, Inc; 6501 William Cannon Drive, Austin, TX 78735